1. Field of the Invention
The present invention relates to a control logic circuit having a characteristic of time hysteresis in a semiconductor memory device, and more particularly to a control logic circuit having a characteristic of time hysteresis when the signals transit from “1” to “0” and from “0” to “1” by connecting two time hysteresis circuits in series.
2. Description of the Prior Art
In general, a digital control logic circuit in a semiconductor memory device generates a glitch (short pulse) during delay time as it passes through a delay unit. A time hysteresis circuit is used for eliminating such a glitch.
The time hysteresis circuit has a characteristic of time hysteresis, and the characteristic of time hysteresis controls transition of a digital control signal for a predetermined time when the digital control signal transits from “1” to “0” or from “0” to “1”. Such characteristic of time hysteresis may eliminate the glitch possibly generated in an output signal when the input signal transits.
FIG. 1 is a diagram showing a conventional time hysteresis circuit.
The conventional time hysteresis circuit comprises latch 1, delay unit 2 and inverter I1.
The latch 1 comprising two NAND gates ND1 and ND2 receives an input signal A(t) and an output signal from the delay unit 2, and outputs an output signal B(t) after latching for a predetermined time. The inverter I1 inverts the output signal B(t) and the delay unit 2 delays an inversion of the output signal B(t) from the inverter I1 for a delay time “td”.
The conventional time hysteresis circuit outputs the output signal B(t) after eliminating the glitch generated when the input signal A(t) transits from “1” to “0”. In other words, the delay unit 2 transmits the inversion of the output signal B(t) to the latch 1 after delaying it for the delay time “td”. The latch 1 latches the input signal A(t) to “1”. However, such characteristic of time hysteresis does not appear when input signal A(t) transits from “0” to “1”.
FIG. 2 is a diagram showing waveforms of signals in the conventional time hysteresis circuit.
The time hysteresis circuit in FIG. 2 outputs the output signal B(t) with the glitch eliminated when the input signal A(t) transits from “1” to “0”. However, if the input signal A(t) transits from “0” to “1”, it will output the output signal B(t) with the glitch not being eliminated.
As a result, the conventional time hysteresis circuit shows a problem to have only one-way characteristic of time hysteresis wherein the input signal A(t) transits from “1” to “0” or from “0” to “1”.